There are many forms of semiconductor-based digital memory. The most common forms-such as static random access memory (SRAM), dynamic random access memory (DRAM), and Flash memory-typically require complicated semiconductor fabrication processes to achieve high memory densities. This goal of high density-measured by the number of bits of data per square centimeter-is desirable for many reasons, not the least of which is to achieve a low cost per bit of storage given the expense of fabrication.
Diode memory arrays are one particular form of semiconductor-based digital memory. U.S. Pat. No. 5,673,218 (“the '218 patent”), for example, describes a memory circuit in which diodes serve as the memory elements. This type of circuit can achieve a low cost per bit of storage due to the simplicity of the semiconductor processing required to fabricate diodes. During fabrication, a diode-only process might require only five or six masks using photolithography, or three or four chemical-mechanical polishing (CMP) and etch steps using topolithography. In contrast, a typical process to create a Flash memory can require 35 masks during fabrication.
FIG. 1 presents a diagram of a diode memory array 100. Most memory applications typically use a dense-array matrix structure for the memory bits themselves and typically implement some type of binary decoding for row and column selection. Binary decoding converts n digital inputs into a maximum of 2n unique outputs, allowing relatively few digital address inputs to select many rows or columns, thereby reducing the complexity of the circuitry needed to access a bit state in the memory array. As depicted in FIG. 2, in one embodiment the row decoder 104′ and column multiplexer 108′ of FIG. 1 may be implemented using AND logic gates and OR logic gates.
Referring again to FIG. 1, the diode memory array 100 includes many bits that are individually accessible by setting the appropriate input address bits on the row decoder 104 and the column decoder 108. Facilitating the off-chip detection of the state of a selected bit without slowing or otherwise affecting the operation of the array is typically a considerable design challenge. Accordingly, it would be desirable to have apparatus and methods that facilitate the off-chip detection of a selected bit state in a memory array.